1. Technical Field
The present invention relates to a delay locked loop (DLL), and more particularly, to a duty cycle correction circuit and a method for duty cycle correction in a DLL.
2. Discussion of the Related Art
In general, in most electronic systems, such as a semiconductor memory device, a video/audio signal processing system or a communications system, a clock is needed for timing control or synchronization. Typically, a delay locked loop (DLL) is used to produce a precise clock signal.
FIG. 1 is a block diagram of a conventional DLL 100. The DLL 100 includes a phase detector 110, a charge pump 120, a loop filter 130, a duty cycle correction circuit 140, a delayer 150, and a buffer 160. The DLL 100 corrects the duty cycle of an input clock signal CLK using an inversion locking scheme or produces an output clock signal DCLK by delaying the input clock signal CLK for a predetermined time. The duty cycle correction circuit 140 corrects the duty cycle of the input clock signal CLK and outputs a corrected clock signal CLKO, controlled by an inversion locking signal IVS. The delayer 150 receives and delays the corrected clock signal CLKO for a predetermined time and outputs the delay result to the buffer 160. Then, the buffer 160 buffers the delay result and outputs the output clock signal DCLK. The phase detector 110 detects the difference in phase between a signal FED output from the delayer 150 and the input clock signal CLK. The charge pump 120 produces a current corresponding to the difference in phase. The loop filter 130 produces a delay control signal VCTL that is proportional to the current generated by the charge pump 120. The length of time that the corrected clock signal CLKO input to the delayer 150 is delayed is determined by the delay control signal VCTL.
Thus, the DLL 100 generates the output clock signal DCLK by using the duty cycle correction circuit 140 according to the inversion locking scheme.
FIG. 2 is a detailed block diagram of the duty cycle correction circuit 140 of FIG. 1. Referring to FIG. 2, the duty cycle correction circuit 140 includes a clock selector 141, an amplifier 142, a buffer 143, and a duty detector 144. The clock selector 141 generates an inversion signal of the input clock signal CLK using an inverter 211, and selectively outputs one of the input clock signal CLK and the inversion signal using a multiplexer 212, controlled by the inversion locking signal IVS. The use of the inversion locking scheme that selectively outputs one of the input clock signal CLK and the inversion signal enables the manufacture of the delayer 150 of FIG. 1 with a smaller number of delay cells. When the corrected clock signal CLKO is fed back to the duty detector 144, the duty detector 144 detects duty correction signals DCC and DCCB and outputs them to the amplifier 142. Then, the amplifier 142 amplifies the input clock signal CLK or the inversion signal selected by the clock selector 141, in response to the duty correction signals DCC and DCCB. The amplified input clock signal CLK is buffered by and output as the corrected clock signal CLKO from the buffer 143. In other words, the corrected clock signal CLKO output from the duty cycle correction circuit 140 is obtained by correcting the duty cycle of the input clock signal CLK. The duty factor represents a percentage (%) ratio of the period of a clock signal at a logic high level to the pulse duration of the clock signal. The duty cycle correction circuit 140 corrects the duty cycle of the input clock signal CLK to 50% and outputs the corrected clock signal CLKO.
However, only the clock selector 141 of the duty cycle correction circuit 140 is controlled by the inversion locking signal IVS. The amplifier 142 and the duty detector 144 operate without regard to the inversion locking scheme. Thus, when the duty factor of the input clock signal CLK is 55%, the duty factor of the clock signal CLK input to the amplifier 142 is between 45% and 55% according to the logic state of the inversion locking signal IVS. For example, the duty factor of the clock signal CLK input to the amplifier 142 is 55% when the clock selector 141 selects the clock signal CLK, and the duty factor of the clock signal CLK is 45% when the clock selector 141 selects the inversion signal of the clock signal CLK. When the logic state of the inversion locking signal IVS changes after the amplifier 142 and the duty detector 144 are stabilized, the amplifier 142 and the duty detector 144, which operate in response to the inversion signal, must operate again to correct the duty cycle of a newly input clock signal. Accordingly, an overall locking time in the DLL 100 is increased, thereby causing a jitter to occur in the DLL 100 and thus causing the DLL 100 to malfunction.